coriolis2 layout expects some specific rules regarding connections between Cells. it has sometimes been the case that only when seeing a layout is it discovered that there is a mistake or it is suboptimal. a redesign of the nmigen HDL would be needed.
although it was not coriolis2 specifically we have had to change the design for SRAM (litex) because the SRAM is a fixed block. additionally the way that pinouts work in niolib required some changes
added a 4k SRAM instance over Wishbone, involved adding "blackbox" atteibute support to coriolis2
verilog and ilang respect cases on names, where vhdl does not. this is causing issues on cosimulation but also name clashes in the P&R. https://gitlab.lip6.fr/vlsi-eda/coriolis/-/issues/37 https://gitlab.lip6.fr/vlsi-eda/coriolis/-/issues/36 https://gitlab.lip6.fr/vlsi-eda/coriolis/-/issues/35 https://gitlab.lip6.fr/vlsi-eda/coriolis/-/issues/34
also c4m-jtag by Staf included here, for the JTAG TAP interface, some debugging and support involved.