Bug 59 - dynamic pipeline chain signalling is timing-critical
Summary: dynamic pipeline chain signalling is timing-critical
Status: RESOLVED INVALID
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Source Code (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL:
Depends on:
Blocks:
 
Reported: 2019-04-07 02:05 BST by Luke Kenneth Casson Leighton
Modified: 2023-09-05 05:42 BST (History)
1 user (show)

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Attachments
screenshot of gtkwave (104.85 KB, image/png)
2019-04-07 02:05 BST, Luke Kenneth Casson Leighton 		Details
screenshot of gtkwave (simpler case) (76.22 KB, image/png)
2019-04-07 04:47 BST, Luke Kenneth Casson Leighton 		Details
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Description Luke Kenneth Casson Leighton 2019-04-07 02:05:41 BST 
Created attachment 5 [details]
screenshot of gtkwave

signalling between two pipelines is somehow getting out of sync (where
one does not)

if the time-differential between d_ready and d_valid is only one clock,
everything is fine.

however if that is extended to 2 clock cycles, the output from pipe2
remains "valid" for one clock longer than it should.

attached annotated drawing.
Comment 1 Luke Kenneth Casson Leighton 2019-04-07 02:10:03 BST 
change the value below from 3 to 2 to generate the succeeding case

class ExampleBufDelayedPipe(BufferedPipeline):

    def __init__(self):
        stage = ExampleStageDelayCls(valid_trigger=3)
        BufferedPipeline.__init__(self, stage, stage_ctl=True,
                                    buffermode=False)
Comment 2 Luke Kenneth Casson Leighton 2019-04-07 04:47:21 BST 
Created attachment 6 [details]
screenshot of gtkwave (simpler case)

found a simpler case, a single pipeline, showing n_i_ready not
really working, which is very strange.
Comment 3 Luke Kenneth Casson Leighton 2019-04-07 07:46:52 BST 
turns out not to be timing at all, was in fact the new
buffermode=False.