Bug 534 - analysis of former variant of SVPrefix to fit onto OpenPOWER with little-to-no modification
Summary: analysis of former variant of SVPrefix to fit onto OpenPOWER with little-to-n...
Status: CONFIRMED
Alias: None
Product: Libre-SOC's first SoC
Classification: Unclassified
Component: Specification (show other bugs)
Version: unspecified
Hardware: PC Linux
: --- enhancement
Assignee: Luke Kenneth Casson Leighton
URL:
Depends on:
Blocks: 213
  Show dependency tree / graph
 
Reported: 2020-11-28 15:15 GMT by Luke Kenneth Casson Leighton
Modified: 2020-11-28 15:59 GMT (History)
1 user (show)

See Also:
NLnet milestone: ---
total budget (EUR) for completion of task and all subtasks: 0
budget (EUR) for this task, excluding subtasks' budget: 0
parent task for budget allocation:
child tasks for budget allocation:
The table of payments (in EUR) for this task; TOML format:

Attachments
Add an attachment (proposed patch, testcase, etc.)

Note You need to log in before you can comment on or make changes to this bug.
Description Luke Kenneth Casson Leighton 2020-11-28 15:15:44 GMT 
https://libre-soc.org/openpower/opcode_regs_deduped/
Comment 1 Luke Kenneth Casson Leighton 2020-11-28 15:59:59 GMT 
the preliminary analysis to fit on top of the forms created for RV show that there is around a 90% match.  things that do not fit or need further analysis:

* st*x instructions (taking 3 read operands and stcix writing to CRs)
* CRio operations (mcrxr and cr* ops) which need de-grouping
* 1W-CRi (read CR, write INT/FP) which needs close inspection
* predication types (one using INTs, one using CRs)

also some operations i have marked as "R-Type" where they only have one
input reg and one output reg (R is actually 2R-1W), ideally a new Form
would be created for these.