To handle the IO, as it is a SoC, there are some very specific GPIO requirements, I wondered if anyone has encountered a libre cell library with the following characteristics, all of which are standard for commercial SoCs and embedded processors: * Pad driver with 10, 20, 30 and 40mA selectable current output * Level shifting so that the pad may be driven by a GPIO VREF and the IO side by an IO VREF. * Incoming GPIO Schmidtt trigger debounce suppression (variable selection, hi med lo frequencies) to stop false IRQ event generation * Edge and Level detection (for IRQs) * Bi-directional IO Pad direction selection capability under user control These can be combined with a pinmux router (under development) and used to construct a commercial grade SoC that is easily comparable to an STM32, ATMEL offering, or an Allwinner SoC or Texas Instruments OMAP. Also, we would like to deploy DDR HyperRAM which is basically Quad SPI upgraded to 8 bit, given a differential clock, and run in DDR Mode. Only 13 IO wires are needed to do 300 mbytes per sec data transfer speeds using a 150mhz clock. This would be an awful lot simpler to implement than DDR3/4, and a verilog HyperRAM interface already exists. Whilst generating a DDR transmit stream is a simple matter of having a clock that operates at 2x the external frequency and putting a flipflop on the output, driving CK with the one ff output and CK# with the inverse, *receiving* DDR data is nowhere near that simple. So in addition to the GPIO above, does anyone know of a libre cell library that can: * take 2 inputs and perform a differential comparison on them and create a digital output * read a value on a *negative* clock edge as well as the positive one * PLL generate a clock that runs at twice the frequency of an incoming DDR clock.
https://www-soc.lip6.fr/wws/arc/alliance-users/2019-04/msg00002.html discussion with jean-paul chaput.
See http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/007699.html
The current IO cell design can be used to get most of the requirements. Some clarification: * There is a level shifted output from the external 3.3V pad voltage to an 1.8V cell output to the core; this signal is asynchronous. It is meant that digital logic is added on this output to implement things like meta-stability prevention, debouncing and IRQ generation. * The block has separate inputs for enabling each of the sink and the source drivers. So if all drivers are disabled the output is high impedance and can driven from an external driver; e.g. in this state the IO cell functions as an input IO cell. * There is a distinction between Schmidtt triggering and signal debouncing. Schmidtt triggering means that the switching threshold is different for a rising edge than for a falling edge. This is to avoid oscillation in the level-shifted core output for slowly moving noisy input signals. With signal debouncing typically stands for the filtering out of mutiple full swing signal swings like one get from push buttons etc. Current implementation of the level-shifting does not include Hysteresis but it should be easy to add for the prototype. As said in first point thoough, signal debouncing is left to the digital logic connected to the level-shifted output of the IO cell.
I want to add that also DDR signaling is left to be implemented in the logic circuit on top of the level-shifted core output. It typically is done by using both a rising edge and a falling edge triggered flip-flop on this output.
(In reply to Staf Verhaegen from comment #4) > I want to add that also DDR signaling is left to be implemented in the logic > circuit on top of the level-shifted core output. It typically is done by > using both a rising edge and a falling edge triggered flip-flop on this > output. this is fantastic, staf. look forward to hearing how the test goes.