On at least ECP5 hardware the ls2/gram DDR3 controller does not function.
This has been traced to multiple defects in the gram HDL along with the ls2 coldboot (libgram) firmware and pin setup. DDR3 is basically functional on the Raptor custom Versa 85 board (with some caveats, see below) as of the following commits: https://gitlab.com/nmigen/nmigen-boards/-/merge_requests/2 https://git.libre-soc.org/?p=gram.git;a=commit;h=ffdcef6b591e73932a97278e011834c8303731cc https://git.libre-soc.org/?p=ls2.git;a=commit;h=8b208495536795b629c72a3d06ef3cd77aab73a0 Status: memtest passes overall, but sometimes the FPGA/DDR3 PLLs/DLLs will fail to lock correctly after programming (noted as significant DQS burst detect shifts during read levelling). This causes memtest to immediately fail with a slew of errors, but repeatedly reprogramming the same bitstream will eventually allow the DDR3 to come up again with no errors at all during either memtest or further operations. My best guess is that the above behavior is due to a questionable DLL lock inside the DDR3 device, and is likely the result of running the device way outside of its specifications (50MHz clock vs. a minimum of 100MHz per the specifications). Efforts to run the DDR3 device at 100MHz and the core at a lower clock frequency will be moved to a new bug report.